For example, image display devices such as an active matrix type (active matrix drive type) liquid crystal display device in which pixels are arranged in a matrix pattern have been widely used. As illustrated in FIG. 23, n lines of data signal lines SL.sub.1 to SL.sub.n and m lines of scanning signal lines GL.sub.1 to GL.sub.m that intersect the data signal lines SL.sub.1 to SL.sub.n are provided in a pixel array 102 of an image display device 101, and a data signal line driving circuit 103 outputs video data D to the data signal lines SL, while a scanning signal line driving circuit 104 selects each of the scanning signal line GL sequentially. Therefore, the video data D is written in a pixel PIX corresponding to a combination of a scanning signal line GL and a data signal line SL, and a display state of each pixel PIX is determined. Incidentally, when there is a need to specify a position, for example, the first scanning signal line GL.sub.1, a subscript numeral representing the position is referred to. On the other hand, when a general term for the lines is referred to or when there is no need to specify a position, a subscript numeral is omitted like the scanning signal line GL.
Here, in the image display device 101, the video data D are supplied as a video signal DAT to each pixel PIX by a time-division system, and the data signal line driving circuit 103 samples the video signal DAT in synchronization with timing signal such as a start signal SPS and a clock signal CKS, amplifies, if necessary, and outputs the video data D to the respective data signal lines.
More specifically, for instance, as shown in FIG. 24 or 25, when the start signal SPS is input to a sampling signal generating section 132 of the data signal line driving circuit 103, a shift register section 133 shifts the start signal SPS in synchronization with the clock signal CKS. Moreover, a buffer section 134 generates sampling signals S.sub.1 to S.sub.n representing sampling timings corresponding to the data signal lines SL.sub.1 to SL.sub.1, respectively, according to outputs N.sub.1 to N.sub.n of the respective stages of the shift register section 133.
On the other hand, in a sampling section 131 of the data signal line driving circuit 103, a sampling circuit AS provided for each data signal line SL determines as to whether the video signal DAT is to be output to the data signal line SL, according to corresponding sampling signal S (/S). As a result, video data D are output to the corresponding data signal lines SL.
Here, as shown in FIG. 26, since a finite signal delay is introduced in the data signal line driving circuit 103, each sampling signal S changes after a delay time td from the clock signal CKS. The delay time td is determined according to the characteristics (mobility, threshold voltage, etc.) and size of a transistor constituting the data signal line driving circuit 103. Thus, the clock signal CKS is applied at such a timing that produces a phase difference ta between the video signal DAT and clock signal CKS by taking the delay time td into consideration, and a sampling time point t101 (time point of the terminating end of pulse: in this case, the time point of the decay of the sampling signal S) is set so that it is a time point in a supply period of the video data D, and more preferably a time point in the vicinity of just before a switching time point t102 of the video data D (td.ltoreq.ta).
In the following description, for the sake of convenience of explanation, the phase difference ta between the video signal DAT and the clock signal CKS is defined as the difference between the switching time point t102 of the video data D and the decay time point of a clock signal CKS used for generating a sampling signal S corresponding to the video data D. Besides, the explanation will be given by discussing the relationship between the sampling signal S.sub.1 of the data signal line SL.sub.1 and the corresponding video data D.sub.1 as an example.
In this case, the sampling circuit AS.sub.1 can sample the video signal DAT at correct timing, and the video data D.sub.1 of a correct value is output to the data signal line SL.sub.1. Moreover, when writing the video data D.sub.1 to the pixel PIX, it is necessary to hold video data D.sub.1 for a predetermined time. Since there is a sufficiently long time before a sampling time point t101 after the video data D.sub.1 is stabilized, the pixel PIX can have a sufficient hold time. As a result, the image display device 101 can display a high quality image without ghosts or blurs.
With the above-mentioned structure, however, for example, if the delay time td is changed due to a variation of the production process, the data signal line driving circuit 103 can not sample the correct video data D, causing a problem that the image quality is lowered by ghosts, blurs of the image, etc.
More specifically, when an actual delay time tdx is longer than the imaginary delay time td due to a change in the delay time td, as illustrated in FIG. 27, there is a possibility that a sampling time point t101x indicated by the sampling signal S.sub.1 comes behind the switching time point t102 of the video data D.sub.1 (tdx&gt;tax) . In this case, since the data signal line SL.sub.1 is supplied with data different from the intended video data D.sub.1 because an inaccurate signal is output during switching from the video data D.sub.1 to D.sub.2, or the next data D.sub.2 is mixed in the data signal line SL.sub.1. As a result, blurs of the image and ghosts occur.
On the other hand, as illustrated in FIG. 28, when the actual delay time tdy is shorter than the imaginary delay time td, the time between the time point t100 at which the video data D.sub.1 is stabilized and a sampling time point t101y indicated by the sampling signal S.sub.1 becomes shorter, and thus there is a possibility that the above-mentioned hold time is not ensured (tdy&lt;tay). In this case, it is impossible to write the video data D.sub.1 of a correct value to the pixel PIX, causing blurs of the image.
The above explanation is given with reference to an example in which each sampled video data D is directly written to the pixel PIX like a point sequential driving method. However, the same problems also occur when a line sequential driving method is employed. Specifically, in the line sequential driving method, once each video data D is held by a sampling and hold circuit, the video data D is applied to each pixel PIX, and the sampling and hold circuit also requires a hold time. Thus, in either case, there is a difference in the timings of the sampling signal S and the video signal DAT, and if the phase difference is out of an appropriate range, blurs of the image or ghosts occur, preventing display of a high quality image.
Therefore, especially in resent years, there are demands for a small-sized, high-resolution image display device and a reduction in the packaging cost. In order to meet such demands, a technique of forming driving circuit such as a data signal line driving circuit and a pixel array integrally on a single substrate has been noted. In such an integrated driving circuit type image display device, in order to increase the display area, a polycrystalline silicon thin film transistor formed on a quarts substrate or glass substrate is often used as an active element. In particular, in the case of a transmissive type liquid crystal display device which has been widely used at present, the substrate is made of the above-mentioned material because the substrate needs to transmit light.
However, in the polycrystalline silicon thin film transistor, the size of crystalline particles and the boundary state vary according to its production conditions. Consequently, transistor's characteristics (the mobility of carrier, threshold voltage, leakage current, etc.) may vary to large extent. For example, the variation of the threshold voltage is within several tens mV for the same substrate. On the other hand, it is not rare that there is a variation of several V between different substrates. Thus, when the polycrystalline silicon thin film transistor is used, the variation in the delay time td becomes larger compared with a substrate using single crystal silicon.
Meanwhile, in the image display device, there is a tendency toward a shorter application cycle of video signal DAT as the resolution is increased. Hence, the allowed difference in the timings between the signals DAT and S tends to decrease, and it is difficult to set the phase difference ta between the video signal DAT and clock signal CKS appropriately in advance. As a result, blurs of the image and ghosts are likely to occur, and an image display device capable of fundamentally limiting such an occurrence is strongly demanded.
Here, for example, Japanese laid-open patent application No. (Tokukaihei) 5-46118 discloses an image display device which detects whether a sampling signal corresponding to video data is present or not, and adjusts the difference in the timings between the video signal and sampling signal according to the result of the detection so as to prevent a displacement of the display position. However, in this structure, it is necessary to use a circuit for specifying the sampling signal corresponding to the video data, thereby requiring a relatively complicated circuit. Moreover, in this image display device, since abnormality can not be detected until the sampling signal corresponding to the video data runs out, the span of adjustable range is a unit of sampling interval, and thus it is impossible to perform highly accurate adjustment. Therefore, this structure can not prevent blurs of the image.